1. Field of the Invention
The present invention relates generally to the transmission, biasing and termination of digital data. More particularly, the present invention presents an I/O cell with programmable active input bias.
2. Description of the Related Art
Today, most electronic systems and many electronic devices (e.g. multichip modules or MCMs) contain several integrated circuits or ICs. Most IC die are comprised of core electronics at its center and input/output electronics, or an I/O ring at its periphery. The core electronics usually perform the primary function of the IC while the I/O ring provides a buffered external interface.
The I/O ring is typically comprised of several (sometimes hundreds) of I/O cells, one for each external signal of the IC. The I/O ring may contain several I/O cell types (e.g. input cells, output cells, tristate output cells and bi-directional cells), one for each external signal type. The transistors of the I/O ring are much larger than those of the core electronics. The core electronics drive devices are contained entirely within the IC die, while the I/O cells typically drive the an external media or devices external to the IC die. Depending on the particular application, the external media is typically referred to as an interconnect, a net, a backplane, a bus, or a bi-directional data line.
I/O cells of different ICs can have different electronic operating characteristics. When two or more I/O cells of different ICs are connected together through a media, the connecting net often requires some form of biasing (pull-up or pull-down) and/or termination to ensure the error-free operation of all the connected I/O cells.
For example, some nets connect a TTL output cell to a CMOS input cell. Such a net requires a pull-up resistor to ensure that the TTL logic high output voltage exceeds the logic high switching threshold voltage of the CMOS input.
Similarly, biasing is typically required in a net connecting two or more tristate output or bi-directional cells. Such a net may require a pull-up or a pull-down resistor to ensure that the net voltage is at a valid logic level when none of the connected I/O cells are driving.
Biasing is also required in nets having physically long trace lengths, such as I/O cells connected across a backplane. When twice the propagation delay of the connecting trace exceeds the edge rates (output rise and fall times) of the connected I/O cells, that trace must be treated like a transmission line. Transmission line effects, such as ringing, overshoots and undershoots, result from I/O driver loading by the characteristic impedance, identified as Z.sub.O, of the connecting trace and signal reflections off impedance discontinuities along the length and especially at the ends of the trace. Such effects can cause data signals to inadvertently cross logic thresholds, which is detrimental or even fatal to device operation.
To minimize these effects, terminations are required at one or both ends of the trace. Terminations have been designed to provide an impedance that closely matches the characteristic impedance of the trace, thus reducing the effective impedance discontinuities and thereby reducing reflections.
As circuit complexity, clock frequencies and edge rates have increased, the number of interconnects requiring biasing and/or termination has increased. Unfortunately, implementing bias and termination requirements with discrete components at the MCM or printed wiring assembly (PWA) level can consume a considerable amount of valuable multichip package (MCP) and/or primed wiring board (PWB) area resulting in increased system size, weight, power requirements and cost.
Currently, some ICs utilize fixed I/O cell biasing at the wafer-level. This biasing usually consists of a single bias resistor with one end tied to the external port of the I/O pad to be biased and the other end tied to a fixed DC level, either power or ground. Unfortunately, The use of fixed wafer-level biasing has been limited because of the varying and often conflicting application dependent bias requirements at the MCM, PWA and/or system levels.